Conventional charge-coupled device (CCD) line imagers use two readout shift registers. The maximum pixel density of this bilinear design is limited by the minimum polysilicon overlap and spacing design rules in the shift registers. Pixel density can be increased by employing a quadrilinear shift register organization to relieve these design rule constraints. See, for example application Ser. No. 285,250, which is assigned to the same assignee as the present invention. Further, reference is made to an article by H. Herbst and H. J. Peleiderer, "Modulation Transfer Function of Quadrilinear CCD Imager", Electronics Letters, Volume 12, Number 25, pps. 676 and 677, 1976. However, as the imager resolution and pixel density increase even further, a new limitation arises due to the narrowing of the CCD parallel transfer channels. That is, the channel between the inner shift register and the outer shift register, in such a quadrilinear register array, becomes narrower due to the increased density of circuitry on a fixed length integrated circuit chip. This narrowing of the charge transfer path from the inner to the outer shift register decreases the minimum potential of the channel which therefore affects the charge transfer efficiency from the inner to the outer shift register. In order to accomplish higher density charge coupled device imagers, this potential barrier problem must be overcome. Once the signals are stored in the quadrilinear registers, prior art devices read out the registers to off chip circuitry for subsequent signal processing.
According to the present invention, a high resolution quadrilinear CCD imager array is utilized which incorporates a unique onchip multiplexing technique. The multiplexing is accomplished in two consecutive steps. First, the two video outputs on either side of the sensor array are multiplexed through a CCD channel. This multiplexed output is then sensed through a source follower, one on either side again. A non-overlapping clocking technique is used to sample and hold the signals on either side and simultaneously the second level of multiplexing is also accomplished, giving a 4:1 video multiplexed output. The final signal is sensed through a second stage source follower circuit. Bad pixel deletion is effected by overriding the sample and hold signal.